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w WM9082 pdm input mono 3w class d speaker driver wolfson microelectronics plc t o receive regular email updates, sign up at http://www.wolfsonmicro.com/ enews production data, august 2012, rev 4.1 copyright ? 2012 wolfson microelectronics plc description the WM9082 is a high-performance sigma-delta class d speaker driver. audio input is supported using a stereo pdm interface; clock and control-c ode detection circuitry supports all of the audio and control functions via a 2-wire interface. the digital audio interface provides excellent noise immunity, eliminating traditi onal input-filtering components. the flexible 2-wire interface minimises the pcb footprint and simplifies software development. the combined audio and control in terface configuration is ideal for enabling the WM9082 to be located close to the speaker; this reduces the l ength of the output connections, giving good emc performance and removing the need for output filter components. the sigma-delta architecture provides good power efficiency and improved emi performance wi th respect to traditional pwm class d designs. a first-order high-pass filter can be selected on the input signal to remove dc offsets and help to prevent speaker damage. other features include a low-power mute state, and output slew-rate control. short-circuit and thermal protection is provided. the WM9082 is supplied in a 9-ball 1.56 x 1.46mm csp package, with 0.5mm ball pitch. features ? sigma-delta class-d speaker driver - 92db snr - ?a? weighted - 2.5w into 4 ? (5v supply, 1% thd) - 1.3w into 4 ? (3.6v supply, 1% thd) - 1.25w into 8 ? (5v supply, 1% thd) - 650mw into 8 ? (3.6v supply, 1% thd ? stereo pdm digital audio input ? supports 32khz, 44.1khz, 48khz sample rates (128fs input) ? automatic left/right channel selection ? first-order high pass filter (hpf) ? rf noise suppression ? pop and click suppression ? programmable output slew rates for low emi ? short-circuit and thermal protection ? 9-ball csp package applications ? mobile handsets ? portable media players (pmp) ? notebooks / laptop computers ? lcd televisions block diagram
WM9082 production data w pd, august 2012, rev 4.1 2 table of contents descript ion ....................................................................................................... 1 ? featur es ............................................................................................................ 1 ? applications ..................................................................................................... 1 ? block diag ram ................................................................................................ 1 ? table of co ntents ......................................................................................... 2 ? pin config uration .......................................................................................... 3 ? ordering info rmation .................................................................................. 3 ? pin descri ption ................................................................................................ 3 ? absolute maximu m ratings ........................................................................ 4 ? recommended operatin g condit ions ..................................................... 4 ? electrical charact eristics ..................................................................... 5 ? terminology ............................................................................................................... 6 ? typical perfo rmance ................................................................................... 7 ? signal timing re quiremen ts ...................................................................... 8 ? pdm audio interf ace timing .................................................................................. 8 ? device des cription ........................................................................................ 9 ? introduction .............................................................................................................. 9 ? pdm audio in terface ................................................................................................ 9 ? device control codes .......................................................................................... 10 ? initial po wer-up .............................................................................................................. .................... 12 ? configuration events .......................................................................................................... ........... 12 ? start-up events ............................................................................................................... .................. 13 ? standby events ................................................................................................................ .................. 14 ? shutdown events ............................................................................................................... ............... 14 ? state transit ion diag ram ...................................................................................................... ......... 15 ? speaker driver ........................................................................................................ 16 ? resets and shutdown .......................................................................................... 16 ? applications in formation ........................................................................ 17 ? recommended external components ............................................................ 17 ? pcb layout cons iderations ............................................................................... 20 ? package dime nsions .................................................................................... 21 ? package diagram for d evices marked lt9 ................................................... 21 ? package diagram for devi ces marked jc5 ................................................... 22 ? important no tice ......................................................................................... 23 ? address: ..................................................................................................................... 23 ? revision hi story ........................................................................................... 24 ?
production data WM9082 w pd, august 2012, rev 4.1 3 pin configuration the WM9082 is supplied in a 9-ball csp format. the pin configuration is illu strated below, showing the top-down view from above the chip. ordering information order code temperature range package moisture sensitivity level peak soldering temperature WM9082ecsn/r -40 ? c to +85 ? c 9-ball csp (pb-free, tape and reel) msl1 260 o c note: reel quantity = 5,000 pin description pin no name type description a1 spkoutp analogue output positive btl speaker output a2 dnc do not connect a3 gnd supply ground b1 spkvdd supply class d output driver supply b2 spkgnd supply ground b3 dvdd supply digital supply c1 spkoutn analogue output negative btl speaker output c2 in2 digital input pdm input (clk or left data input) c3 in1 digital input pdm input (clk or right data input)
WM9082 production data w pd, august 2012, rev 4.1 4 absolute maximum ratings absolute maximum ratings are stress ratings only. pe rmanent damage to the device ma y be caused by continuously operating at or beyond these limits. device functional operat ing limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std- 020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specif ied in ordering information. condition min max class d output driver supply voltage (spkvdd) -0.3v 7.0v digital supply voltage (dvdd) -0.3v 2.5v voltage range digital inputs gnd - 0.3v dvdd +0.3v operating temperature range, t a -40oc +85oc storage temperature after soldering -65oc +150oc recommended operating conditions parameter symbol min typ max unit class d output driver supply spkvdd 3.2 3.6 5.5 v digital supply dvdd 1.35 1.8 2.0 v ground spkgnd, gnd 0 v note: 1. all digital and analogue grounds must always be within 0.3v of each other.
production data WM9082 w pd, august 2012, rev 4.1 5 electrical characteristics test conditions spkvdd = 3.6v, dvdd = 1.8v, spkgnd=gnd = 0v, t a = +25 o c, load = 4 ? +33h, 1khz signal, clk=6.144mhz (128fs), fs =48khz unless otherwise stated. parameter symbol test conditions min typ max unit speaker driver signal to noise ratio snr a-weighted 92 db idle channel noise a-weighted 66 ? v rms total harmonic distortion + noise thd+n p o = 625mw -70 db output power (thd+n = 1%) p o r l = 4 ? , spkvdd = 3.6v 1.3 w r l = 4 ? , spkvdd = 5.0v 2.5 r l = 8 ? , spkvdd = 3.6v 0.65 r l = 8 ? , spkvdd = 5.0v 1.25 speaker load resistance (see note 1) 3 ? speaker load capacitance (see note 1) direct connection to spkoutp+spkoutn 200 pf psrr (spkvdd) psrr 200mv (peak-peak) 217hz idle digital audio input while in the on state 70 db power efficiency r l = 4 ? , p o = 625mw, spkvdd = 3.6v 82 % r l = 8 ? , p o = 625mw, spkvdd = 3.6v 86 clocking (in1 or in2) clk input fs = 48khz 6.144 mhz fs = 44.1khz 5.6448 fs = 32khz 4.096 digital input (in1 or in2) input high level (see note 1) 0.7 x dvdd v input low level (see note 1) 0.3 x dvdd v input capacitance (see note 1) 10 pf input leakage -0.9 0.9 ? a other parameters pop-free start-up time ?off? state to ?on? state (see figure 3) 1 ms shutdown time ?on? state to ?off? state (see figure 3) 1 ms
WM9082 production data w pd, august 2012, rev 4.1 6 parameter symbol test conditions min typ max unit power consumption quiescent current (WM9082 in the ?on? state; clk enabled; data input is idle channel data.) i dvdd 0.6 ma i spkvdd r l = 4 ? 8 ma r l = 8 ? 8 standby current (WM9082 in the ?standby? state; clk enabled; data input is repeated control code.) i dvdd 250 a i spkvdd 200 a shutdown current (WM9082 in the off state; clk and data inputs disabled.) i dvdd 0.6 a i spkvdd 0.05 a note 1: guaranteed by design; not production-tested. terminology 1. signal-to-noise ratio (db) ? snr is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20hz to 20khz. (no auto-zero or mute function is employed). 2. total harmonic distortion (db) ? thd is the difference in level between a 1khz reference sine wave output signal and the sum of the harmonics of the output signal. the amp litude of the fundamental frequency of the output signal is compared to the rms value of the sum of the harmonics and expressed as a ratio. 3. total harmonic distortion plus noise (db) ? thd+n is the difference in le vel between a 1khz reference sine wave output signal and all noise and distortion products in t he audio band. the amplitude of the fundamental reference frequency of the output signal is compared to the rms val ue of all other noise and distortion products and expressed as a ratio. 4. power supply rejection ratio (db) ? psrr is a meas ure of ripple attenuation between a power supply rail and a signal output path. with the signal path idle, a small sine wa ve ripple is applied to power supply rail. the amplitude of the supply ripple is compared to the amplitude of t he output signal generated and is expressed as a ratio. 5. all performance measurements are carried out with 20khz aes17 low pass filter for distortion measurements, and an a-weighted filter for noise measurement. failure to use such a filter will result in higher thd and lower snr and dynamic range readings than are found in the electrical characteristics. t he low pass filter removes out-of-band noise; although it is not audible, it may affect dynamic specification values.
production data WM9082 w pd, august 2012, rev 4.1 7 typical performance typical speaker driver thd+n per formance is shown below for 8 ? and 4 ? load conditions. plots are shown for typical spkvdd supply voltage conditions. (dvdd=1.8v in all cases.) 0.00 0.01 0.10 1.00 10.00 0.10 1.00 thd + n rat io (% ) output power (w) thd+n vs. output power load = 8 ? + 33h spkvdd ? =5.5v spkvdd ? =3.6v 0.00 0.01 0.10 1.00 10.00 0.10 1.00 thd + n rat io (% ) output power (w) thd+n vs. output power load = 4 ? + 33h spkvdd ? =5.5v spkvdd ? =3.6v
WM9082 production data w pd, august 2012, rev 4.1 8 signal timing requirements pdm audio interface timing clk (input) data (input) t lh t lsu t rh t rsu t cy t cl t ch test conditions spkvdd=3.6v, dvdd=1.8v, spkgnd=gnd=0v, t a = +25 o c, unless otherwise stated. parameter symbol min typ max unit pdm audio interface timing clk cycle time t cy 140 162 250 ns clk pulse width high t ch 60 81 ns clk pulse width low t cl 60 81 ns data set-up time to clk rising edge (left channel data) t lsu 10 ns data hold time from clk rising edge (left channel data) t lh 7 ns data set-up time to clk falling edge (right channel data) t rsu 10 ns data hold time from clk fa lling edge (right channel data) t rh 7 ns
production data WM9082 w pd, august 2012, rev 4.1 9 device description introduction the WM9082 is a high performance sigma-delta cla ss d speaker driver designed for a range of high performance, low-power audio applicati ons. it is packaged in a 9-ball csp. the device comprises two digital input pins, wh ich support the clk and data inputs of the pdm audio interface. automatic left/right channel select ion is provided using aut omatic detection of the input configuration. the pdm audio interface also supports decoding of sil ent control codes which can be used to configure the WM9082 or to select the low power, standby operating state. the WM9082 incorporates a selectable first-order hi gh-pass filter for removing dc offsets and to help prevent speaker damage. input sample rates of 32khz, 44.1khz and 48khz are supported. the sigma-delta architecture of the class d output driver provides good power efficiency and improved emi performance with respect to traditional pwm class d designs. the class d speaker driver is powered from spkv dd in the range 3.2v to 5.5v. the driver can deliver 2.5w output into a 4 ? load. the WM9082 is suitable for posit ioning very close to the external loudspeaker. the differential (btl) outputs can connec t directly to the loudspeaker with no other external components required. short-circuit and thermal prot ection is also provided. the WM9082 is supplied in a 9-ball 1.56 x 1.46mm csp package, with 0.5mm ball pitch. pdm audio interface the WM9082 supports a stereo pdm audio interface, comprising a clk wire and a data wire. two channels of audio data are multiplexed on the data wire; the WM9082 speaker driver selects either the left channel data or the right channel data depending on the hardware configuration of the interface connection. each channel of pdm audio data consists of a stream of 1-bit data samples; the bit rate is 128 x fs, where fs is the sample frequency of the received audio signal. note that pdm is a ?pulse density modulation? coding, where the si gnal amplitude is represented by the density of logic 1?s in any window of consecutive data bits. two audio channels are interleaved on the pdm interfac e as illustrated in figure 1. the left channel data is read at the rising edge of clk; the right channel data is read at the falling edge of clk. see ?signal timing requirements? for specific timing requirements. clk input data input (left & right channels interleaved) l r l r l r left channel input l l l right channel input r r r figure 1 pdm audio interface
WM9082 production data w pd, august 2012, rev 4.1 10 the channel selection for the WM9082 speaker driver is implemented automatically by sensing which of the inputs pins is clk and which pi n is data, as defined in table 1. to ensure correct channel selection, it must be ens ured that the data input is disabled whenever the clk input is disabled. if the data input signal is present when clk is disabled, this may result in incorrect channel selection. input configuration speaker channel clk = in1 data = in2 left clk = in2 data = in1 right table 1 pdm channel selection if stereo operation is required, using two WM9082 speak er drivers, then this can be implemented very easily, by cross-connecting the clk and data wires on the two speaker drivers, as illustrated in figure 2. figure 2 stereo pdm operation the channel detection is determined automatically at device start-up, and also after any period when the clk input has stopped. device control codes when power supplies are present (see ?reco mmended operating conditions?), and audio data is input at the audio interface, the WM9082 powers up and the class d speaker driver is enabled. the WM9082 selects either the left or right channel data as described in ?pdm audio interface?. the WM9082 can be controlled usi ng specific data sequences, know n as control codes, received over the pdm audio interface. each control code is a ?zero? code when decoded as audio data. therefore, the control codes can be transmitted to the WM9082 in the form of silent audio data, but the codes will be recognised by t he WM9082 as control instructions. the WM9082 control codes are defined in table 2 and table 3. the control codes are 8-bit codes, which must be transmitted lsb first. the page 1 control codes (see table 2) are valid when transmitted consecut ively for the required number of times. the page 2 control codes (see table 3) are valid only when preceded by the ?page 2 access? instruction (ie. page 1, code 6). in most cases, the control codes are only valid if they are received more than 32 times consecutively (see below for further details). for greatest reliab ility, however, it is recommended that the host device always transmits control codes at least 64 times w henever it is desired to send a control instruction to the WM9082. if the WM9082 is configured to receive left channel data, then it will only respond to control codes received on the left channel of the pdm interface. si milarly, if the WM9082 is configured to receive right channel data, then it will only respond to control codes received on the right channel.
production data WM9082 w pd, august 2012, rev 4.1 11 id function description control code code 1 start up (3.6v spkvdd) fast start-up for default spkvdd aa code 2 standby disable class d output 66 code 3 emi control 1 invert sr[1] f0 code 4 32khz mode control select 32khz sample rate mode 8b code 5 high pass filter control disable 2hz high pass filter 39 code 6 page 2 access enable page 2 control codes 56 code 7 reserved d1 code 8 reserved d2 code 9 start up (3.6v spkvdd) start-up for spkvdd = 3.6v d4 code 10 start up (5.0v spkvdd) start-up for spkvdd = 5.0v d8 table 2 WM9082 page 1 control codes id function description control code code 1 reserved aa code 2 reserved 66 code 3 performance control 1 invert pc1[0] f0 code 4 reserved 8b code 5 reserved 39 code 6 reserved 56 code 7 reserved d1 code 8 reserved d2 code 9 emi control 2 invert sr[0] d4 code 10 performance control 2 increment pc2[1:0] d8 table 3 WM9082 page 2 control codes the output driver slew-rate control is configurabl e using the sr[1] and sr[0] bits. these fields are defined in table 4. the slew-rate contro l code sequences are described in table 6. sr[1] sr[0] output slew rate (output rise / fall time) 0 0 5ns (default) 0 1 10ns 1 0 20ns 1 1 40ns table 4 output slew rate control bits the output driver operating mode is configurable using the pc1[0] and pc 2[1:0] bits. these fields are defined in table 5. selected operating mode cont rol code sequences are described in table 6. pc1[0] pc2[1:0] description 1 00 best psrr 1 01 (default) 1 10 1 11 0 xx best snr table 5 operating mode control bits
WM9082 production data w pd, august 2012, rev 4.1 12 as noted above, the WM9082 control codes are only valid when they are transmitted consecutively for the required number of times. the valid contro l codes can be used to control the operating state of the WM9082 and also to select different operating modes. the ?page 2 access? control code enables the page 2 control codes for the next control code only; the page 1 codes will apply again fo r any subsequent control code(s). the state transitions and operat ing modes are described below. initial power-up when a valid clk signal is first detected on in1 or in2, the WM9082 powers up to the ?standby? state. the WM9082 will remain in this state until a ?s tart-up event? is detected, or until the clk signal is removed. configuration events in the standby state, the WM9082 can be conf igured (if required) using the control code sequences listed in table 6. note that these control code sequences are only va lid when the WM9082 is in the standby state; it is not possible to configure the devic e whilst simultaneously sending audio data. the following features are configurable in the standby state: ? sample rate (33khz, 44.1khz or 48khz) ? input path high pass filter (hpf) ? output slew rate control ? operating mode (psrr vs snr control) the cut-off frequency of the input path hpf, w hen enabled, is around 2hz, assuming a 48khz audio sample rate (clk = 6.144mhz). the operating mode selections provide differ ent options for snr vs psrr optimisation.
production data WM9082 w pd, august 2012, rev 4.1 13 the control code sequences are listed in table 6. description control code select 32khz sample rate 32 x code 4 disable the input path hpf 32 x code 5 select 10ns output slew rate 32 x code 6 32 x code 9 select 20ns output slew rate 32 x code 3 select 40ns output slew rate 32 x code 3 32 x code 6 32 x code 9 select ?best psrr? mode 32 x code 6 32 x code 10 32 x code 6 32 x code 10 32 x code 6 32 x code 10 select ?best snr? mode 32 x code 6 32 x code 3 table 6 WM9082 configuration events if none of these control code sequences is received, then the WM9082 is configured for the following default operating conditions: ? sample rate is 44.1khz or 48khz ? input path high pass filter (hpf) enabled ? output slew rate is 10ns ? default psrr and snr (see ?ele ctrical characteristics?) note that the default operating conditions are onl y restored on power-up or following a period when the clk input is stopped. start-up events the WM9082 class d output is enabled whenever pdm audi o data is detected at the input pins, or when a valid start-up control code is detected. the WM9082 start-up is selected under any of the conditions described in table 7. each of these conditions results in a transition to the ?on? state. note that, if spkvdd > 4.3v, then it is recommended to start up the WM9082 using code 10; this ensures that the device is optimally configured for the higher spkvdd level. note that, when the start-up transition occurs as a result of pdm audio data, then the WM9082 will be enabled in whichever mode had previously been selected (if any). in the case where the ?on? state has not previously been selected, then t he default (spkvdd = 3.6v) mode is chosen.
WM9082 production data w pd, august 2012, rev 4.1 14 condition description 4 x code 1 fast start-up for default spkvdd condition (spkvdd = 3.6v) 32 x code 9 start-up for spkvdd = 3.6v 32 x code 10 start-up for spkvdd = 5.0v pdm audio data fast start-up table 7 WM9082 start-up events standby events the WM9082 class d output is disabled whenever the pdm input data is interrupted, or when a valid standby control code is detected. the WM9082 standby transition is selected during normal operation (ie. from the ?on? state?) under any of t he conditions described in table 8. each of these conditions results in a transition to the ?standby? state. condition description 32 x code 2 standby command - selects standby state 64 x any control code selects standby state error condition selects standby state (an error condition is detected if >24 consecutive 1?s or >24 consecutive 0?s is received on the pdm audio interface.) table 8 WM9082 standby events note that repeated instances of any control code will not cause more than one state transition until audio data or a different control code has been re ceived. this prevents the WM9082 from cycling between the ?on? state and the ?standby? state in the event of repeated control codes. shutdown events if the clk input is not present at any time, this re sults in a transition to the ?off? state. the WM9082 will remain in the ?off? state until the clk input restarts.
production data WM9082 w pd, august 2012, rev 4.1 15 state transition diagram the WM9082 operating states and transitions are illustrated in figure 3. figure 3 state transition diagram
WM9082 production data w pd, august 2012, rev 4.1 16 speaker driver the speaker outputs spkoutp and spkout n operate in a btl configurat ion. these pins provide a differential output for direct connection to the louds peaker. in a typical application, no other external components are required for the loudspeaker connection. the sigma-delta architecture of the class d driver is more linear and power efficient than traditional pwm implementations, resulting in reduced power consumption and improved emi characteristics. the speaker driver is disabled during start-up and following receipt of selected control codes which can be used to configure the WM9082. the driver is automatically re-enabled on receipt of any audio data. resets and shutdown a power on reset circuit ensures correct star t-up and shut-down when the dvdd supply rail is enabled or disabled. the WM9082 is held in the ?off? state when there is no clk signal detected on the in1 or in2 pins; the shutdown current in the ?off? state is noted in the ?electrical characteristics? section. short circuit and thermal protection is also provided. in the event of an output short-circuit or an over- temperature condition, the WM9082 will protect itself by disabling the class d speaker driver. the WM9082 will automatically recover and continue norma l operation when the fault condition is cleared.
production data WM9082 w pd, august 2012, rev 4.1 17 applications information recommended external components power supply decoupling electrical coupling exists particu larly in digital logic systems where switching in one sub-system causes fluctuations on the power supply. this effect occurs bec ause the inductance of the power supply acts in opposition to the c hanges in current flow that are caused by the logic switching. the resultant variations (or ?spikes?) in the power supply voltage can cause ma lfunctions and unintentional behaviour in other components. a decoupling (or ?bypass?) capacitor can be used as an energy storage component which will provide power to the decoupled circuit for the dur ation of these power supply variations, protecting it from ma lfunctions that could otherwise arise. coupling also occurs in a lower-frequency form when ripple is present on the power supply rail caused by changes in the load current or by limitat ions of the power supply regulation method. in audio components such as the WM9082, these variat ions can alter the per formance of the signal path, leading to degradation in signal quality. a decoupli ng (or ?bypass?) capacitor can be used to filter these effects, by presenting the ripple voltage wi th a low impedance path that does not affect the circuit to be decoupled. these coupling effects are addressed by plac ing a capacitor between the supply rail and the corresponding ground reference. in the case of sy stems comprising multiple power supply rails, decoupling should be provided on each rail. the recommended power supply decoupling capacitor s for WM9082 are listed below in table 9. power supply decoupling capacitor dvdd 0.1 ? f ceramic spkvdd 4.7 ? f ceramic table 9 power supply decoupling capacitors all decoupling capacitors shoul d be placed as close as po ssible to the WM9082 device. due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacit ance across the required temperature and voltage ranges in the intended application. for most applicati on the use of ceramic capacitors with capacitor dielectric x5r is recommended. class d speaker connections the WM9082 incorporates a class d speaker driver, which offers high amplifier efficiency at large signal levels. as the class d output is a sigma- delta modulated signal, the choice of speakers and tracking of signals is important for ensuring good performance and reducing emi. the efficiency of the speaker drivers is affe cted by the series resistance between the WM9082 and the speaker (e.g. pcb track loss and inductor esr) as shown in figure 4. this resistance should be as low as possible to maximise efficiency.
WM9082 production data w pd, august 2012, rev 4.1 18 figure 4 speaker connection losses the class d output requires external filtering in order to recreate the audio signal. this may be implemented using a 2 nd order lc filter, or else may be achieved by using a loudspeaker whose internal inductance provides t he required filter response. an lc filter should be used if the loudspeaker characteristics are unk nown or unsuitable, or if the length of the loudspeaker connection is likely to lead to emi problems. a suitable lc filter implementation is illustrated in figure 5. figure 5 class d output filter components a simple equivalent circuit of a l oudspeaker consists of a serially connected resistor and inductor, as shown in figure 6. this circuit provides a low pass filter for t he speaker output. if the loudspeaker characteristics are suitable, then the loudspeaker it self can be used in place of the filter components described earlier. this is know n as ?filterless? operation. figure 6 speaker equivalent circuit for filterless operation
production data WM9082 w pd, august 2012, rev 4.1 19 for filterless class d operation, it is important to ensure that a speaker wi th suitable inductance is chosen. for example, if we know the speaker impedance is 8 ? and the desired cut-off frequency is 20khz, then the optimum speaker inductance may be calculated as: 8 ? loudspeakers typically have an inductance in the range 20 ? h to 100 ? h, however, it should be noted that a loudspeaker inductance will not be cons tant across the relevant frequencies for class d operation (up to and beyond the class d switching frequency). the class d outputs of the WM9082 operate at much higher frequencies than is recommended for most speakers; care should be taken to ensure that the cut-off frequency of the loudspeaker?s filtering is low enough to suppress the high frequency energy of the class d switching and, in so doing, to prevent speaker damage. a simple test can be used to confirm if the loudspeak er is compatible with filterless operation. under quiescent input conditions (idle digital audio input while in the on state), the spkvdd current is measured with the speaker disconnected, and meas ured again with the speaker connected. if the spkvdd current increases by more than 10ma when the speaker is connect ed, then the speaker alone is not effective as a filter, and it is re commended to consider changi ng the speaker or adding lc filter components. recommended external components diagram figure 7 provides a summary of recommended external components for WM9082. note that the actual requirements may differ according to the specific target application. figure 7 WM9082 recommended external components diagram
WM9082 production data w pd, august 2012, rev 4.1 20 pcb layout considerations poor pcb layout will degrade the performance and be a contributory factor in emi, ground bounce and resistive voltage losses. all external co mponents should be placed as close to the WM9082 device as possible, with current loop areas kept as small as possible. class d loudspeaker connection long, exposed pcb tracks or connection wires will emit emi. the distance between the WM9082 and the loudspeaker should therefore be kept as short as possible. w here speakers are connected to the pcb via a cable form, it is recommended that a shie lded twisted pair cable is used. the shield should be connected to the main system, with care taken to ensure ground loops are avoided. further reduction in emi can be achieved using pcb ground (or v dd) planes and also by using passive lc components to filter the class d switch ing waveform. when passive filtering is used, low esr components should be chosen in order to mini mise the series resistance between the WM9082 and the speaker, maximising the power efficiency. lc passive filtering will usually be effective at reducing emi at frequencies up to around 30mhz. to reduce emissions at higher frequencies, ferrite beads can also be used. these should be positioned as close to the device as possible. these techniques for emi reducti on are illustrated in figure 8. emi low esr low esr long, exposed tracks emit emi short connection wires wi ll reduce emi emission shielding using pcb ground (or vdd) planes will reduce emi emission lc filtering will reduce emi emission up to around 30mhz ferrite beads will reduce emi emission at frequencies above 30mhz. WM9082 WM9082 WM9082 WM9082 WM9082 spkoutp spkoutn spkoutp spkoutn spkoutp spkoutn spkoutp spkoutn spkoutp spkoutn figure 8 emi reduction techniques
production data WM9082 w pd, august 2012, rev 4.1 21 package dimensions package diagram for devices marked lt9 dm085.b b: 9 ball w-csp package 1.560 x 1.460 x 0.635mm body, 0.50 mm ball pitch notes: 1. primary datum -z- and seating plane are defined by the spherical crowns of the solder balls. 2. a1 corner is identified by ink/laser mark on top package. 3. ?e? represents the basic solder ball grid pitch. 4. this drawing is subject to change without notice. 5. follows jedec design guide mo-211-c. a1 0.230 d d1 e e1 e 1.000 bsc 1.460 0.275 1.000 bsc 0.500 bsc 1.560 dimensions (mm) symbols min nom max note a 0.635 a2 0.388 0.400 0.412 3 f 1 0.652 0.618 0.235 0.240 0.225 h 0.320 a1 corner top view e d 2 detail 2 detail 2 a a2 a1 z 1 solder ball e1 a detail 1 c b e e bottom view 1 32 f 1 f 2 h 3 d1 0.05 4 x 4 4 f 2 detail 1 1.550 1.450 1.470 1.570
WM9082 production data w pd, august 2012, rev 4.1 22 package diagram for devices marked jc5 dm085.c b: 9 ball w-csp package 1.570 x 1.470 x 0.649mm body, 0.50 mm ball pitch notes: 1. primary datum -z- and seating plane are defined by the spherical crowns of the solder balls. 2. a1 corner is identified by ink/laser mark on top package. 3. ?e? represents the basic solder ball grid pitch. 4. this drawing is subject to change without notice. 5. follows jedec design guide mo-211-c. a1 0.212 d d1 e e1 e 1.000 bsc 1.470 0.273 1.000 bsc 0.500 bsc 1.570 dimensions (mm) symbols min nom max note a 0.649 a2 0.387 0.400 0.413 3 f 1 0.688 0.610 0.249 0.286 0.223 h 0.311 a1 corner top view e d 2 d eta il 2 detail 2 a a2 a1 z 1 solder ball e1 a detail 1 c b e e bottom view 1 3 2 f 1 f 2 h 3 d1 0.025 4 x 4 4 f 2 d eta il 1 1.545 1.445 1.495 1.595 0.261 0.361
production data WM9082 w pd, august 2012, rev 4.1 23 important notice wolfson microelectronics plc (?wol fson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at t he date of shipment. wolfson reserves the right to make changes to its products and s pecifications or to discontinue any produc t or service without notice. customers should therefore obtain the latest version of relevant informati on from wolfson to verify that the information is current. testing and other quality control techniques are utilized to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless requi red by law or regulation. in order to minimize risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or proc edural hazards. wolfson is not liable fo r applications assistance or customer product design. the customer is solely responsible for its se lection and use of wolfson products . wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to re sult in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or pr ocess in which its products or services might be or are used. any prov ision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. wolfson is not liable for any unauthorised [ alteration of such information or for any reliance placed thereon. any representations made, warranties giv en, and/or liabilities accepted by any pers on which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
WM9082 production data w pd, august 2012, rev 4.1 24 revision history date rev description of changes page changed by 05/07/10 1.0 first release 20/04/11 2.0 product status updated to preliminary technical data 21/04/11 2.0 updated pinout changing vrefc to dnc. all associated diagrams and tables also updated to reflect the change 1, 4, 16, 18 wf 28/04/11 2.0 psrr typical electrical c haracteristics values added 5 bm 03/05/11 2.0 in description, removed ?the recommended configuration requires only 3 external capacitors? 1 wf 12/08/11 2.1/2.2 electrical characteristics updated. additional control codes defi ned for slew rate control & performance mode. updates to filterless speaker description & recommendations ph 15/09/11 2.2 electrical characteristics updated default slew rate / oper ating mode conditions updated ph 25/10/11 3.0 product status updated to pre-production jmacd 18/05/12 4.0 electrical characteristics updated typical performance graphs added ph 10/08/12 4.1 package diagram dm085c added. jmacd

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